module mod48(
Clk,
Reset_n,
Q,
clock,
sh_cp,
st_cp,
ds
    );
input Clk;
input Reset_n;

output [7:0]Q;
output clock;

output sh_cp;
output st_cp;
output ds;

reg [24:0]cnt;
reg CP;

wire ld_n;
wire rco;
wire [31:0]disp_data;

parameter MCNT=12_499_999;

assign clock=CP;
assign ld_n=~(Q==8'b0010_1111);
assign disp_data={24'b0,Q};


always@(posedge Clk or negedge Reset_n)
if(!Reset_n)
    cnt<=25'd0;
else if(cnt==MCNT)
        cnt<=25'd0;
     else
        cnt<=cnt+1'b1;

always@(posedge Clk or negedge Reset_n)
if(!Reset_n)
    CP<=0;    
else if(cnt==MCNT)
        CP=~CP;
     else
        CP<=CP;

x74ls161 x74ls161_inst0(
.CL_n(Reset_n),
.CP(CP),
.A(4'b0000),
.EP(1'b1),
.ET(1'b1),
.LD_n(ld_n),
.Q(Q[3:0]),
.RCO(rco)
);

x74ls161 x74ls161_inst1(
.CL_n(Reset_n),
.CP(CP),
.A(4'b0000),
.EP(rco),
.ET(1'b1),
.LD_n(ld_n),
.Q(Q[7:4]),
.RCO()
);

hex_top hex_top_inst0(
.clk(Clk),
.reset_n(Reset_n),
.disp_data(disp_data),
.sh_cp(sh_cp),
.st_cp(st_cp),
.ds(ds)
);
    
endmodule
